Field
Embodiments described herein relate to semiconductor packaging. More particularly, embodiments relate to packages including 3D stacked die.
Background Information
The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. Additionally, while the form factor (e.g. thickness) and footprint (e.g. area) for semiconductor die packaging is decreasing, the number of input/output (I/O) pads is increasing.
Various multiple-die packaging solutions such as system in package (SiP) and package on package (PoP) have become more popular to meet the demand for higher die/component density devices. In an SiP a number of different die are enclosed within the package as a single module. Thus, the SiP may perform all or most of the functions of an electronic system.
A 3D stacking implementation such as chip on wafer (CoW) includes mounting of die onto a support wafer, followed by singulation of stacked die SiPs. A 3D stacking implementation such as wafer to wafer (W2W) includes mounting of a top wafer onto a bottom wafer, followed by singulation of stacked die SiPs. Both of the conventional 3D stacking implementations require that one of the package level tiers (e.g. mounted die, or die within wafer) to be bigger or equal to the other tier. For example, CoW may involve the singulated area of the support wafer being bigger than the die mounted on the support wafer, while W2W may involve equal areas of the singulated wafers.